Design and implementation of parallel floating point matrix multiplier for quaternion computation

Many surveys done on software developments for quaternion computation identifies floating point matrix multiplier as the most time consuming process. The floating point matrix multiplier is a highly procedure oriented process and involves computation of many partial products and storing them for final result computation. For above reason we propose a parallel matrix multiplier design which accelerates the computational speed. In this design the nested loops of software based matrix multiplier are converted into parallel computing blocks on FPGA using modified Systolic array for matrix multiplication, which best matches the inherent parallelism of FPGA architecture. The architecture utilizes only 14% of the IO resource and is 100 times faster compared to software implementation when implemented on FPGA Spartan-6 of 12MHz clock.