The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory

A multiple-stage simulation procedure identifies, for the first time, the location of secondary electrons that very efficiently produce gate currents in flash EEPROMs. The simulation method incorporates both electron and hole Monte Carlo analysis to calculate this secondary electron gate current without introducing additional fitting parameters. (I/sub g//I/sub d/) continues to increase for smaller channel length (50/spl times/ from L/sub g/-03.39 to 0.12 /spl mu/m) and higher substrate doping (more than 6/spl times/ when doubled) in scaled, low-power flash memory.