Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance

This paper contributes the first study of manufacturing variation on interconnect timing performance in a high speed microprocessor. Also new in this paper is a methodology using timing analysis in conjunction with post-extraction net adjustment to account for interconnect structure variation (e.g., that arising due to pattern dependencies); this methodology is efficient enough to enable thousands of nets to be analyzed for variation and is compatible with current CAD tools.