Single damascene and dual damascene contact etch at Sub28nm logic technology

FinFET technology has been chosen for extending CMOS scaling beyond 28nm node. It can improve short channel control through a fully depleted fin, reduce random dopant fluctuation, improve mobility, lower parasitic junction capacitance and improve area efficiency. The non-SAC (self-aligned contact) local interconnection is introduced for the device connection. As the pitch shrinkage beyond immersion resolution capability, the contact loop pattern definition has been divided into several parts, so-called contact plug, M0P and M0G. Contact plug metal connects active area, M0P metal stands on contact plug metal, M0G connects metal gate and M1 or M0 to form local interconnection. Both of the single damascene and dual damascene approaches can be applied in the contact loop. In this paper, we tested the single damascene and dual damascene approaches, and investigated the process window enlargement from the point of view of LWR (line width roughness) reduction, CD (critical dimension) shrinkage and profile optimization.