Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

We have developed a novel high speed dynamic threshold voltage MOSFET named LCSED for ultra low power operation. This was realized using sidewall elevated drain. The LCSED achieved the following excellent characteristics as compared to the bulk-DTMOS which we proposed earlier: 60% reduced occupation area; 65% reduced junction capacitance; 67% reduced forward leakage current between shallow-well and source/drain; lower transistor series resistance; smaller short channel effect; higher drive current. These effects realize ultra low power high speed operation.