Capacitor-on-metal/via-stacked-plug (CMVP) memory cell for 0.25 /spl mu/m CMOS embedded FeRAM

A capacitor-on-metal/via-stacked-plug (CMVP) memory cell was developed for 0.25 /spl mu/m CMOS logic embedded FeRAM. Using 445/spl deg/C MOCVD Pb(Zr,Ti)O/sub 3/ process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables cell size reduction (3.2 /spl mu/m/sup 2/ for 1T1C), minimum process damage on ferroelectric, and low manufacturing cost.