Intrinsic stress effects on the warpage of silicon substrate during thin film deposition, photolithography and etching processes

Wafer warpage become more and more critical in the semiconductor industry. As is well known, the wafer warpage is caused by the mismatch of thermal expansion coefficients (CTE) and the intrinsic stress formation in thin film during thin film deposition; unfortunately, the intrinsic stresses are not easily characterized. In order to evaluate quantitatively the intrinsic stress at deposition temperature, and understand its variation during the photolithography and etching flow processes, an experimental and numerical approach is developed in this paper. Wafer warpage is measured at room temperature using a laser interferometer. The finite element model is constructed by using the 2D axisymmetric hypothesis. Intrinsic stress effects were modeled under the same temperature used to deposit the layer. The simulation both with and without intrinsic stresses are assumed in order to compare with experimental results. The results of warpage obtained from our FEM model with intrinsic stress assumption give good agreement with the experimental measurement.