Thermo-mechanical simulation to optimize the integration of a BST stacked MIMIM capacitor

For the last decade, paraelectric Ba
_x
Sr
_1-x
TiO
₃
(BST) thin films have been especially studied to fabricate MIM capacitor for capacitance tuning applications. This paper describes the mechanisms of cracks apparition under BST stacked MIMIM capacitors (Metal Insulator Metal Insulator Metal) built on silicon substrate. The methodology used in this study to have a further understanding of this phenomenon is to investigate 2D process simulations, based on an elastic model. Hence, it could be evidenced that the gap between the extreme stress levels induced by an annealing performed at the end of the capacitor manufacturing is the main contributor in the crack formation. Then, the change from silicon to a sapphire substrate was implemented to avoid cracks in the real process integration. Finally, the capacitor devices could be tested and were demonstrated to exhibit better electrical specifications.