Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond

The defects induced by the thermo-mechanical stress in the device fabrication process are correlated with device characteristics of 1 Gb DRAM. To identify the defect formation in the thermal process, we modeled the cumulative thermo-mechanical stress (CTMS) throughout the shallow trench isolation (STI) integrated DRAM process, and performed computer simulation using ABAQUS. The defect-free stress level was extracted from the relationship between the cumulative shear stress and electrical device characteristics, and then applied to optimizing thermal annealing process to obtain the defect-free process condition for the fabrication of 1 Gb DRAM and beyond.