ESD circuit synthesis and analysis using TCAD and SPICE

This paper describes the development of a SPICE sub-circuit model for an avalanche triggered SCR used for ESD protection. The approach for developing the model is presented, including the extensive use of TCAD tools, which provides physical insight. This is the first SPICE model presented for an avalanche triggered SCR demonstrating accurate terminal behavior under both steady state and transient triggering conditions. It is intended for use in a design environment for examining ESD circuit behavior at the chip level.