Source-Underlapped GaSb–InAs TFETs With Applications to Gain Cell Embedded DRAMs

In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb-InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both nand p-type GaSb-InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green's function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 μs at V
_DD
= 0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages.