Improving the statistical variability of delay-based physical unclonable functions

Physical Unclonable Functions (PUFs) are circuits which exploit the statistical variability of the fabrication process to create a unique device identity. PUFs have been used in the design of cryptographic primitives for applications like device authentication, key generation and intellectual property protection. Due to its small cost and design simplicity, delay-based Arbiter PUFs (APUFs) have been considered a cryptographic engine candidate for the integration into low-cost IoT devices (e.g. RFID tags). Although APUFs have been extensively studied in the literature, not much work has been done in understanding how to improve its response variability using VLSI design techniques. This paper uses extensive AMS 350nm SPICE-based Monte-Carlo simulation to analyze how the proper selection of arbiter element and gate sizing can affect the delay variability of APUFs. Experimental results show that the combination of the appropriate arbiter and gate sizing configuration can considerably improve the Hamming Weight distribution of the APUF response, thus resulting in more reliable and less biased designs.