Analysis and system-level design of a high resolution incremental ΣΔ ADC for biomedical applications

This paper presents an analysis and system-level design of an incremental sigma-delta converter (IΣΔ ADC) in order to explore a possible solution to low power multi-channel applications. The problem of using classic ΣΔ ADCs for applications which require time multiplexed signals will be discussed. The IΣΔ ADCs are characterized for resetting all memory elements present in ΣΔ modulator core and digital filter in the beginning of each conversion. The modulator architecture consists of a 4th loop filter using feedforward summation topology and its coefficients were provided through a simple algorithm which establishes the minimum required number of clock cycles for one conversion. SIMULINK building blocks were used to model the non idealities, such as sampling jitter, switches' and op-amps' thermal noise, finite bandwidth, slew rate and finite DC gain. The results show that the modulator achieves a signal-to-noise ratio (SNR) greater than 100 dB for 80 kHz signal bandwidth divided for 20 channels.