Template-based QC-LDPC decoder architecture generation

This paper presents an automated template-based approach for layered QC-LDPC architectures. The underlying idea is to be able to generate any number of fairly optimized hardware designs with only a minimum effort required by tuning high level parameters (parity check matrix, number of AP-LLR messages being processed at a time, etc.). Having chosen a partially parallel architecture, template design effort has been concentrated in two directions: distributed control across the LDPC decoder for modularity and versatility, and datapath design in order to support any given parallelism at processing node level. All user inputs are propagated by the proposed automated flow for all design phases: (i) Verilog HDL LDPC architecture (ii) test-benches and verification environments (iii) evaluation step (BER/FER, average iterations, cost, throughput) of the LDPC decoder architecture. We present the results for the architectures generated for dv = 3, dv = 4 regular QC-LDPC code, as well as for the WiMAX (1152,2304) irregular code, with different levels of parallelism at processing node level.