A novel approach to design a redundant binary signed digit adder cell using reversible logic gates

Redundant Binary Signed Digit (RBSD) number system motivates the researchers to design high speed processing devices. RBSD adders can perform fast addition of two numbers due to the phenomenon of the absence of carry calculation and manipulation requirement. This paper presents a novel approach to design RBSD adder cell using some basic reversible logic gates such as feynman, BJN and peres gate. This adder cell design can be considered as an initial work for the low loss as well as high speed digital systems. Moreover, there is scope of further optimization of various performance parameters to enhance the efficiency of the designed adder circuit. This proposed designed is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.