Study of approximate compressors for multiplication using FPGA

Multiplication is an integral part of most of the signal processing applications. Most of the multipliers require large space, consume more power and are the main source of delay in computer arithmetic. Approximate multiplication is extensively used in applications such as multimedia and image processing, which require higher speed and can tolerate some error and imprecision. We are studying accurate compressor and two approximate compressors for Dadda multiplier. We are comparing the hardware complexity of designs, critical path delay, and error rate and power consumption for the three designs.