Oversampled Sigma Delta ADC decimation filter: Design techniques, challenges, tradeoffs and optimization

With the rapid developments in the IC technology and signal processing oversampled Sigma Delta (ΣΔ) ADCs have become the absolute choice among the competent data converters due to their efficient architectures and ease of implementation in VLSI technology. Their efficiency lies in the schemes to decrease area, reduce power consumption and ways to improve frequency response without putting any stress on design cost and compatibility factor. They have their own issues which need to be improved or optimized in order to run neck by neck for being compatible for the efficient designs. Decimation filter being the important block in the ΣΔ ADCs needs some improvements in some areas for meeting the demands of an efficient design. This paper presents a brief overview of ΣΔ ADCs, various techniques of decimation filter design and different architectures, design methods, and practical issues, solutions and tradeoffs.