Multi-objective genetic algorithm-based optimization of an asynchronous data-flow security processor

The architecture of a recently proposed Globally Asynchronous Locally Synchronous (GALS) processor dedicated to security programs is considered. Operations are performed using a number of Functional Units (FUs) grouped into a number of Execution Regions (ERs) working with independent clocks. The selection of the number of ERs as well as the distribution of the FUs among regions is approached as a multi-objective optimization problem with the objective functions selected as area, delay, and energy. This problem is solved using the NSGA-II algorithm. The obtained solutions are compared with those obtained in the case of operating all regions with the same clock. It is shown that for the case of AES encryption and with high communication delay overheads the synchronous case achieves a better performance. However, by reducing these overheads and speeding up the instruction region, execution delay with asynchronous operation can be reduced to 56% of the delay in the synchronous case.