MAD Gates—Memristor Logic Design Using Driver Circuitry

Memristors have recently begun to be explored in arithmetic applications. However, all prior designs for memristor-based gates have had shortcomings in terms of scalability, applicability, completeness, and performance. In this brief, a new low-power gate design, i.e., memristors-as-drivers gates, is proposed, which overcomes each of these issues by combining sense circuitry with the IMPLY operation. By sensing the values of the input memristors as the driver for the output memristor, the delay is reduced to a single step for any Boolean operation, including xor. The area is reduced to at most three memristors for each gate and consumes only 30 fJ. An ${N}$-bit ripple carry adder implementation is proposed, which uses these gates to achieve a total delay of ${N}+1$ with an area of 8${N}$ memristors and their drivers. The individual bits of the proposed adder can be also pipelined, reducing the latency to four steps per addition.