Minimum multiplier implementation of a comb filter using lattice wave digital filter

The minimum hardware and low power dissipation are the main concern for efficient filter implementation. A method to design and implement the comb lattice wave digital filter with only one multiplier, small area and low power dissipation is proposed. Lattice wave digital filter is used for filter realization due to its excellent properties. A design level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The filter is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.