FPGA implementation of second-order difference plot for epileptic seizure detection in EEG signals

Field-programmable gate arrays (FPGAs) are being extensively used for a wide range of digital applications due to their flexibility and reprogrammability. This paper presents a FPGA implementation of the second-order difference plot (SODP) technique which can be used for the classification of ictal and seizure-free electroencephalogram (EEG) signals. Empirical mode decomposition (EMD) can break down an EEG signal into simple oscillatory modes called intrinsic mode functions (IMFs). The hardware design developed takes a sampled IMF of an EEG signal as input and generates its SODP while simultaneously calculating the 95 percent confidence ellipse area of the SODP. The ellipse area can be used as a parameter for detecting epileptic seizures in EEG signals. The digital circuit was designed in the Vivado integrated development environment (IDE) using Verilog hardware description language (HDL) and a Xilinx Artix-7 xc7a100tcsg324 FPGA was used to verify operation of the physical implementation. The hardware was tested on EEG data made publicly available by the University of Bonn and the results were found to be consistent with MATLAB simulations.