Solving constraints in FPGA detailed routing using SMT

In this paper, we present a new approach for solving the FPGA detailed routing problem using Satisfiability Modulo Theories (SMT). SMT allows problem formulation in richer first-order logic fragments. The detailed routing constraints are directly mapped to a chain of the standard SMT-LIB2 assertions of equality and inequality predicates. The SMT formulation eliminates the need to encode the net track segments into Boolean variables and to decode the routing solution. Moreover, it is independent of the channel width. Using SMT assertion stack capabilities, the detailed routing problem can be explored for various FPGA architecture models with different routing resources capabilities without the need to reformulate the whole constraints. SMT capability for solving objective functions is utilized to find the optimal minimum channel width. Experimental results show that the proposed SMT-based approach provides higher modeling flexibility and execution speedup compared to the SAT-based approach.