SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder

The most recent video compression standard is the High Efficient Video Coding (HEVC). It was created with the goal of reaching better videos compression compared to the existing ones. One of the most time-consuming modules of HEVC encoder is the Sum of Absolute Transform Differences (SATD), which is used in intra prediction mode decision and in Fractional pixel Motion Estimation (FME) modules. This paper proposes a dedicated architecture for SATD, based on 2-D 8×8 Hadamard Transform, which is divided into 1-D horizontal and 1-D vertical transforms. The architecture was synthesized to ASIC 45 nm technology and to FPGA. The results show that the whole SATD architecture consumes a total cell area of 12231 μm2, dissipates 3765.6 μW of total power and consumes 50.85 pJ of energy per SATD operation.