A highly scalable vector oriented ASIP-based multi-standard digital receiver

The design of next generation wireless communication terminals encounters a number of difficulties due to having conflicting design objectives. On the one hand, users' equipments have to support multiple wireless communication standards. On the other hand, they have to attain high performance in terms of throughput, latency and SQNR, while maintaining low power consumption. Application Specific Instruction-Set Processor (ASIP) is a promising approach to support the flexibility required by wireless equipment, while maintaining a high performance and low power consumption. In this paper, we introduce a highly scalable vector oriented ASIP-based baseband digital receiver to support large class of wireless communication algorithms. The data-path of the proposed engine comprises an array of identical reconfigurable cells that can work simultaneously. Hence, the different performance requirements by different standards can be handled by changing the number of cells. The ASIP cell structure achieves both high reconfigurability and resource utilization, which makes it capable of performing a wide range of elementary operations, used in most wireless communication algorithms efficiently.