A Time-Interleaved Multimode $\Delta\Sigma$ RF-DAC for Direct Digital-to-RF Synthesis

A multimode delta-sigma (ΔΣ) RF digital-to-analog converter (RF-DAC) is proposed for direct digital-to-RF synthesis. The proposed circuit uses a single clock frequency (f
₈
) and provides a ΔΣ modulator (DSM) that operates in bandpass (BP) and highpass (HP) modes to synthesize signals around f
₈
/4, f
₈
/2, or 3f
₈
/4. The on-chip 14 bit second-order DSM implements an array of 1 bit pipelined subtract functions to generate 3 bit f8 rate RF-DAC input data. Analog interleaving via a second 3 bit DAC is used to reject the first DAC image, simultaneously doubling the usable bandwidth of the HP DSM and increasing the SNR. Calibration circuits are added to the DAC to compensate for amplitude and timing variations. The proposed RF-DAC is implemented in 130 nm SiGe BiCMOS with an area of 0.563 mm
²
. Measurements at f
₈
= 2 GHz yield an output power of -0.6 dBm with 76.2 dB signal-to-image-rejection ratio (SIRR), 76.2 dB SFDR over a 100 MHz bandwidth, -80 dBc IM3, -67.2 dB WCDMA ACLR, and -66.4 dBc LTE ACLR. Changing f
₈
to 3 GHz allows frequencies of 2.25 GHz to be generated with output power of -16.6 dBm, 65.2 dB SFDR, -62 dBc IM3, -59.3 dB WCDMA ACLR, and -59.2 dBc LTE ACLR.