Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices

Forecasts project that by 2020, there will be around 50 billion devices connected to the Internet of Things (IoT), most of which will operate untethered and unplugged. While environmental energy harvesting is a promising solution to power these IoT edge devices, it introduces new complexities due to the unreliable nature of ambient energy sources. In the presence of an unreliable power supply, frequent check pointing of system state becomes imperative and recent research proposed the concept of in-situ check pointing by employing ferroelectric RAM (FRAM), an emerging non-volatile memory, as unified memory. Even though an entirely FRAM-based solution provides reliability, it is energy-inefficient compared to SRAM due to a higher access latency. On the other hand, an entirely SRAM-based solution is highly energy efficient, but is unreliable in the face of power loss. This paper advocates an intermediate approach in hybrid FRAM-SRAM MCUs that involves judicious memory mapping of program sections to retain the reliability benefits provided by FRAM while performing almost as efficiently as an SRAM-based system. We propose an energy-aware memory mapping technique that maps different sections to the hybrid FRAM-SRAM MCU such that energy consumption is optimized without sacrificing reliability. Our technique consists of eM-map, which performs a one-time characterization to find the optimal memory map for the functions that constitute a program (this makes our solution portable across platforms) and energy-align, a novel HW/SW technique that aligns the system's powered-on time intervals to function execution boundaries, which results in further improvements in energy efficiency and performance. Our experiments using the MSP430FR5739 microcontroller demonstrate a significant performance improvement of up to 2x and energy reduction of up to 20% over a state-of-the-art FRAM-based solution.