Verilog implementation of double precision floating point division using vedic paravartya sutra

Divider unit is one of the essential parts of processor design. Usually Divider design is of meticulous interest since the design area utilization is more and divider usage in various applications like cryptography, digital signal Processing, logical computations, encryption and decryption algorithms. Compact and efficient Divider design has always been a challenging task. This paper proposes the implementation of double precision floating point division algorithm using the Paravartya division technique of ancient Indian Vedic mathematics and comparisons are presented with respect to the design of division through multiple subtractions double precision floating point divisor. The division algorithm for double precision floating point division using Verilog Code is introduced and implemented in Artix-7 FPGA series. Results simulated by the proposed algorithm shows reduction in power consumption by 36.63% as well as design space by 29.08% when compared to multiple subtractions double precision division method.