A 3–10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC

Continuous-time data conversion and continuous-time DSP are an interesting alternative to conventional methods of signal conversion and processing. This alternative does not suffer from aliasing, shows superior spectral properties (e.g., no quantization noise floor), and enables event-driven flexible signal processing capabilities using digital circuits, thus scaling well with technology. However, this approach has so far been limited by the power dissipation of the continuous-time ADC. We present a novel continuous-time ADC architecture suitable for this approach, that allows a programmable, highly compact, and power-efficient circuit implementation, while preserving the benefits of continuous-time ADC/DSP systems. In the process, first-order quantization error spectral shaping has been added, which improves the baseband SNDR. Implemented in 0.65-V 28-nm FDSOI process, the 0.0032mm
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ADC achieves 32-42 dB SNDR over a 10-50 MHz bandwidth while consuming 24μW, giving an FOM of 3-10 fJ/conversion-step. The ADC shows signal-amplitude-dependent power dissipation with a zero-input power of 8 μW.