Macroscopic Mechanical Constitutive Characterization of Through-Silicon-via-Based 3-D Integration

Through-silicon-via (TSV)-based 3-D integrated circuit (IC) integration (herein termed 3-D TSV IC technology) generally comprises several TSV chips, each of which may be composed of a significant number of continuously aligned TSVs and microjoints with complex geometry and structure. Directly assessing their thermal-mechanical responses and hence reliability through the finite-element analysis (FEA) can be very challenging. In this paper, an elasticity/FEA-based macroscopic mechanical constitutive characterization technique incorporated with a global/local FE (GLFE) submodeling approach is proposed for effectively simulating the thermal-mechanical behaviors of 3-D TSV IC packages. The focus of the macroscopic mechanical constitutive characterization is placed on the prediction of the effective coefficients of thermal expansion (CTEs) of the TSV chips. The predicted effective CTEs are compared with those of two simplified analytical estimates based on rule-of-mixture and energy methods. In addition, the dependence of the effective CTEs on some essential geometry parameters is also examined, by which approximate mathematical formulas in the form of global response surface (RS) are constructed using an RS methodology. The proposed methodology is tested on a high-density, fine-pitch 3-D TSV IC package, where its effectiveness is demonstrated through a comparison with those of two baseline FEA models. Results show that the proposed methodology could efficiently and accurately predict the thermal-mechanical behaviors of the 3-D TSV IC package. In addition, the predicted effective CTEs of the TSV chips show a strong dependence on the geometry of the TSV chip structure. At the permissible range of the geometry parameters, the TSV chip structure reveals a CTE transverse isotropy, where the out-of-plane ones tend to be larger than the in-plane ones.