Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology

This brief presents a multiternary digit (trit) multiplier design in carbon-nanotube field-effect transistor (CNTFET) technology using unary operators of multivalued logic. The proposed structure is based on the classical Wallace multiplier and includes a novel ternary multiplexer design requiring only a small number of CNTFETs. Two ternary full-adder configurations are also proposed based on an examination of the multiplier structure. In addition, the design includes a new single-trit multiplier which requires 67% less CNTFETs compared to a recent design. HSPICE simulations reveal low power-delay product for the proposed designs for different choices of drive strength. Furthermore, the designs are comparable to prior works with respect to noise margin.