Embedded system of the iris segmentation module

Iris Recognition is one of the important biometric recognition systems that identify people based on their eyes and iris. Most modern systems are currently deployed on traditional sequential digital systems, such as a computer. However, modern advancements in reconfigurable hardware, most FPGAs (Field-Programmable Gate Arrays) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. So that, many authentication applications can be carried out by portable devices. In this paper, we implement the new version C of the iris segmentation [1], which is developed from the Osiris system, in a Cyclone II FPGA DE2_70 FPGA. In the first step, as a software application using Nios II, In the second step, as a hardware-software application using Quartus II and SOPc Builder to accelerate the time processing, after the use of Hardware accelerators. The results show that with a clock speed of 50MHZ from image of 640*480, the gain in the time execution is 768 ms, from the total time needed by the software solution running on the same embedded microprocessor in the architecture.