FPGA-based H.264 Video Decoder in RTP payload format

This paper presents the implementation of a hardware-based H.264 Video Decoder employing real-time transport protocol (RTP). The supported video resolution is 176×144 at 30 fps. The hardware selected is the Lattice ECP3 FPGA at a frequency of 1.5 MHz. The FPGA process flow is used to validate the implementation. Cadence NC-Verilog tool is used for simulation and Lattice Diamond tool is used for Synthesis, Map, Place and Route and Static Timing Analysis. Place and Route result shows that 60% of the slices are utilized. Trace report shows that the maximum frequency of the system is 19.5 MHz.