The influence of the drain multiplication current on latchup behavior

A method is described for determining the maximum operating voltage of a NMOS transistor in a CMOS technology before latch-up occurs. The drain multiplication current and the shunting well resistance are very important parameters for simulating the initiation of the parasitic thyristor. Measurement results show the influence of the well resistance and the gate length for transistors processed on bulk wafers and on epi wafers. Good agreement between simulations and experimental results is obtained.<
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