The development of a 0.25 /spl mu/m CMOS receiver for GSM

To meet GSM standards, critical building blocks in the RF front-end must provide low noise figures, high linearity and predictable gain, while requiring as few external passive components and consume as little current as possible. This paper presents a transceiver front-end in 0.25 /spl mu/m CMOS that includes a 11 mA LNA with 1.9 dB NF, a 6 mA mixer with 12.6 dB NF (SSB), a 71 MHz IF amplifier with programmable gain between -20 and 60 dB in 2 dB steps and an I/Q demodulator with an image rejection of 43.5 dB. The performance of the chip, together with an overall power consumption of 25 mA, makes this chip competitive with most existing BJT solutions.