Series memristors: A hardened memory cell design against read faults

In this paper, a new approach is presented to address the read disturbance and mitigate the need of whole data refreshing. The basics of scheme is to construct a memory cell using two series memristors, where their directions are similar. The direction of current is to increase resistivity. To save bit value `1', memristors are programed inversely, one of them is set to minimum memristance and the other one to maximum. According to Kirchhoff's voltage law, a great deal of voltage falls on memristor with high memristance, making no change to its memristance, and a small portion of voltage falls on memristor with low resistivity having a small effect on its memristance. To save bit value `0' both memristors are programed to the maximum resistivity. Comparing the voltage across the memristors indicates the saved bit. However, the need of whole data refreshing caused by read disturbance will be reduced more than 10 times depending on read circuit and its sensibility.