Electrical characterisation of horizontal and vertical gate-all-around Si/SiGe nanowires field effect transistors

This paper report the technological routes used to build horizontal and vertical gate all-around (GAA) Field-Effect Transistors (FETs) using both Si and SiGe NanoWires (NWs). Horizontal Si and SiGe nanowires FETs are characterized in back gate configuration. Vertical devices using Si nanowires (NWs) show good characteristics with an I
_ON
/I
_OFF
ratio close to 10
⁶
and sub-threshold slope around 145 mV/decade. Finally, vertical SiGe devices also obtained with the same technological process present an I
_ON
/I
_OFF
ratio from 10
³
to 10
⁴
but also poor dynamics which can be explained by the high interface traps density.