A Reconfigurable DT $\Delta \Sigma $ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers

The popularity of fourth generation (4G) cellular communication technology, and the concurrent predominance of second (2G) and third generation (3G) systems have made multi-standard wireless transceivers a necessity. This paper describes the system level planning, the architectural design, and the VLSI implementation of a reconfigurable discrete-time ΔΣ ADC for a multi-standard 2G/3G/4G wireless receiver. We present an optimized switched-capacitor loop filter implementation that maximizes the achievable sampling rate by deploying an early regeneration of the quantizer. Reconfigurability is mainly realized at the architectural level by adapting the oversampling ratio and the quantizer resolution, depending on the mode, to achieve the required dynamic range. Implemented in a 130 nm CMOS technology, and occupying an area of 0.31 mm
²
, the modulator runs at a maximum sampling rate of 450 MHz. The ADC achieves 87 dB and 63 dB DR in a 100 kHz and 25 MHz bandwidth, respectively. The effective resolution ranges from 13.2 bit to 9.7 bit at a scalable power consumption between 3.4 mW and 56.7 mW from a single 1.2 V supply. An open loop reference buffer is embedded on-chip to generate the required reference voltage levels (without the need for external components) making the modulator suitable for fully integrated cellular transceivers.