Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell)

Fabricated on a 14nm process technology node, the Intel Core
^TM
M and the 5
^th
generation Core
^TM
processors (code named Broadwell) improve energy efficiency over the previous 22nm generation by up to 2.5x. Numerous optimizations were used in the analog circuits to achieve this power reduction. PLLs were designed to have low analog V
_min
to enable operation without the use of a dedicated voltage rail. This enabled system level power optimization that yielded 28% lower power on that rail. Zero Distribution Latency to Full Distribution Latency (ZDL-to-FDL) mode was introduced in the PLLs, reducing clock distribution power and achieving ~150mV reduction in the clock distribution supply's V
_min
. DDR power was reduced by 3x through the use of VTT termination, instead of the traditional Center Tapped Termination (CTT). A new package Cstate (C7+) was introduced to reduce integrated voltage regulator losses under low load conditions. Duty cycling of the thermal sensor reduced average power 10x relative to the prior generation while a fast wakeup technique reduced convergence time to ~10us.