A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network

This paper presents a highly linear dual-band mixed-mode polar power amplifier fully integrated in a standard 65nm bulk CMOS process. An ultra-compact single-transformer passive network provides dual-band optimum load-pull impedance matching, parallel power combining, and double even-harmonic rejection without any tunable element or band selection switch. The mixed-mode architecture leverages both digital and analog techniques to suppress the AM-AM and AM-PM distortions and achieves high linearity. As a proof-of-concept design, the dual-band mixed-mode polar power amplifier is implemented in a 65nm CMOS process. We demonstrate the peak output power of +28.1dBm/+26.0dBm with the PA drain efficiency of 40.7%/27.0% at 2.6/4.5GHz. Measurement with 1MSym/s 256-QAM signal achieves rms EVM of 2.05%/1.03% with the average output power of +21.51dBm/+19.27dBm at 2.35/4.7GHz. The measured 2
^nd
-harmonic rejection for the 2.35GHz signal is 37.7dB.