Defect and temperature dependence of tunneling in InGaAs/GaAsSb heterojunctions with varying band alignments

Summary form only given. In this work, we utilize two-terminal measurements of conductance slope as a means to probe the nature of tunneling at the interface without convolution of three-terminal parasitic effects such as gate-oxide traps or parasitic leakage pathways resulting from the more complicated geometry of a three-terminal device. The conductance slope gives an approximation to a transistor response in two terminals. [6,7] By removing three-terminal parasitics, the true nature of tunneling and its dependence on materials defects can be seen. Additionally, it allows for a comparison to be made between tunneling with and without gate-oxide traps present to better determine if such defects could be playing a role in the observed temperature dependence of published devices. In this work, we epitaxially grow InAs/GaSb and InGaAs/GaAsSb of varying alloying compositions and hence, varying band alignments. We study the effect of material defects on conductance slope at different band alignments via the effect of buffer layers to grade the strain. We also examine the temperature dependence of conductance slope to make important insights into the true nature of tunneling at the interface in the absence of oxide traps.