Reaching the limits of CMOS technology

Summary form only given. The remarkable characteristic of transistors that fuels the rapid growth of the information technology industry is that their speed increases and their production cost decreases as their size is reduced. No other product in manufacturing has this characteristic over the vast range of size reduction demonstrated by the transistor. Current transistors are 20 times faster and occupy less than 1% of the area of those built 20 years ago. It seems intuitively obvious that continued transistor area reduction by a factor of 2 every 3 years, as in Moore's Law, cannot be sustained forever. However, predictions of the size reduction limit or even of the pace of size reduction have proven to elude the most insightful scientists. The predicted limit has been dropping at nearly the same rate as transistor size. The current dominant transistor technology in large ICs, including microprocessors, is CMOS. By studying CMOS scaling, we conclude that IC performance increase will indeed lessen as transistor size is further reduced from what is currently achievable. The major technology elements considered in CMOS scaling projection are: (1) lithography to enable manufacture of devices with smaller dimensions, (2) transistor design for higher performance at smaller dimensions, (3) smaller wiring for on-chip interconnection, (4) stable circuits, (5) more productive design automation tools, (6) greater memory cell density, and (7) manageable capital costs. We review each of these elements and present our conclusions in this presentation.