Design of parallel FFT architecture using Cooley Tukey algorithm

In this paper, a parallel FFT architecture is proposed to give an efficient throughput and less energy consumption with the help of Cooley Tukey algorithm for radix 8. In this algorithm the DFT of N size is divided into smaller sizes of N/2 and repeated until final DFT scalars are found. It divides the DFT in even index and odd index term. The computation time which is calculated by the pre defined formula (Nlog
₂
(N)) is reduced by the use of parallel architecture. Energy is defined as power used per unit time. Parallel architecture helps to perform number of operations simultaneously. As less time is required, the energy is efficiency is increased. The aim of this paper is to check throughput and efficiency using Cooley Tukey algorithm for higher radix. The recent trends of this algorithm is development of FPGA that is Field Programmable Gate Array as it can perform signal processing tasks in parallel, execute pipeline structure as well as speed up the computation of tedious algorithms. The main advantage of Cooley Tukey algorithm is that it reduces arithmetic computations as well as fast processing. As this algorithm divides the DFT into smaller DFTs, it can be combined with any other algorithm simultaneously.