An approach to the design of a deterministic jitter-free dual-chamber brady pacer in an ICD using hardware and software cooperation

The authors present a methodology, which applies to hardware/software co-design and co-simulation in the context of a deterministic, jitter-free (no early or latent stimulus), dual-chamber bradycardia pacer in an implantable-cardioverter-defibrillator. Using a hardware description language (Verilog XL), a simulation environment is developed that accurately allows software generated in the microprocessor's native language to be run in the simulated environment. Behaviour that is not allocated to silicon or microprocessor software (heart model, external hardware, etc.) is simulated only at the behavioral level. The simulation environment provides an emulated debugging capability that allows all designers to interactively observe the hardware and software functions in non-realtime for behavioral correctness and faults. Finally, a verification technique is applied that provides automatic flagging and logging of the system's state on an event-by-event basis.