Optimisation of gate circuit layout to suppress power/drive interaction

Due to the common impedance coupling between power and drive circuit in the high speed switch (IGBT or MOSFET) based power converters, a parasitic voltage is induced in the gate circuit during switching phases. This phenomenon leads to an increase of switching losses, and is at the origin of EMC problems. In this paper an alternative to the special emitter/source pin is proposed. This is based on the mutual effect between power and drive circuit. In this respect, a specific layout for the gate circuit is presented, the novel structure cancels power/drive interaction. This layout provides a large gate inductance which is undesirable, an optimisation of the structure is thus performed to reach the best compromise: not too high gate inductance and diminution of power/drive interaction. To validate the efficiency of the proposed structure, experimental and simulation results are presented.