Parameterizable Ethernet Network-on-Chip Architecture on FPGA

With the number of cores increase in systems-on-chip (SoC), bus-based approach began facing challenges to support internal communication. An alternative that has been explored is the network-on-chip (NoC), an approach that proposes to use common network knowledge on SoC projects internal communication. The standards non-adoption in the NoC components development however has delayed its wide diffusion. This paper focuses on providing a complete NoC architecture, configurable and customizable following the Ethernet standard. The three NoC basic modules, Network Adapter (NA), Link and Switch, are implemented. The results were obtained using a Stratix IV FPGA. The evaluation metrics used for NoC validation are silicon area and latency. The experiment using two NAs, two cores and one Switch needed 7310 FPGA ALUTs which corresponds to 4% of their logical resources. The Ethernet frame (64 Bytes) transmission spent 422 clock cycles on FPGA.