Gated low-power clock tree synthesis for 3D-ICs

In this paper, we minimize 3D clock power using shutdown gates to selectively turn off unnecessary clock activities. In 3D-IC, shutdown signals require large-sized Through-Silicon-Vias(TSVs), so we propose a simulated annealing(SA) based algorithm along with a force-directed TSV placer to decide the selection of shutdown gates and the locations of TSVs under layout whitespace constraint. Furthermore, we recognize optimal power saving is achieved when the clock tree itself is designed simultaneously with the shutdown network. Experimental results show that our heuristic decreases the total clock power by more than 20% with less than 1.5% wirelength overhead while ensuring zero clock skew.