Design of priority encoding based reversible comparators

Reversible logic has emerged as an alternate design technique to the conventional logic, resulting in lower power consumption and lesser circuit area. Comparators are a key element in most digital systems. In this paper we propose two new reversible comparator designs based on the concept of priority encoding. The designs consist of mainly the Toffoli gates with both positive and negative control lines. The designs are optimized to reduce the quantum cost and delay. The proposed designs offer more than 40% improvement in delay over the existing serial comparator and the equation based comparator. We also propose modifications to the existing serial comparator and the equation based comparator for optimized performance.