A 14-bit 70MS/s pipeline ADC with power-efficient back-end stages

A 14-bit SHA-less pipeline ADC based on 2.5-bit per stage architecture is proposed. Implemented in TSMC 0.18μm CMOS process, the proposed ADC achieves an ENOB of 11.34-bits and consumes 41 mW power at 70 MS/s thereby achieving an FOM of 226fJ/conversion-step which compares favorably with state-of-the-art work. The low-power consumption is attributed to the careful design of back-end stages based on a novel gain-boosting recycling folded-cascode amplifier.