High-throughput hardware implementation for motion estimation in HEVC encoder

This paper presents a highly parallel motion estimation architecture for High Efficiency Video Coding (HEVC) encoder. The proposed architecture has 16 processing units operating in parallel to calculate the sum of absolute difference values of all possible variable prediction block sizes. Hence, it calculates the bit cost regarding every partition in order to find the best matching candidate in terms of bit cost. The proposed unit processes block sizes from 4×4 up to 64×64. The proposed architecture was prototyped, simulated and synthesized using 65nm TSMC CMOS technology. At 720 MHz clock frequency, the proposed architecture processes 2K (1920×1080) resolution at 30 fps with ±27 (55×55) pixel search range using full search algorithm. Moreover, the proposed architecture is a flexible one and it can be used with different search algorithms to process higher resolutions such as 4K (3840×2160) resolution with 30 fps rate. To the best of our knowledge, the proposed architecture is one of the first ASIC motion estimation architectures in the literature for HEVC.