Memory Architecture Quad Core Risc Processor on Altera FPGA De Nano Board

This project work presents a framework to design a shared memory and QUAD-Core Processor, on a programmable platform. Complete flow is proposed by a programming model and architecture. The effectiveness of shared memory blocks is demonstrated by implementing on FPGA. The aim of the project is to develop an architecture, design, implement and test QUAD-Core Processor on Alter a DE1 FPGA Board. Four Processors are connected in star topology and share common memory for program and data. Depending o the application the Processor is expected to run at MHz, with effective instruction cycle speed of MHz.